Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device includes 
     a source region  4 , a channel region  8 , a drain region  5    
     and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region  22  is formed between the channel region  8  and drain region  5  so as to be shallow below the gate electrode  7 A (first N −  layer  22 A) and deep in the vicinity of the drain region  5  (second N −  layer  22 B). 
     This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.

This is a divisional of application Ser. No. 09/512,520, filed Feb. 24,2000 now U.S. Pat. No. 6,255,154.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method ofmanufacturing it, and more particularly to LD (Lateral Double Diffused)MOS transistor technology which is used for a high voltage element fore.g. liquid crystal driving IC.

2. Description of the Related Art

Now, an LDMOS transistor structure refers to a structure in whichimpurities with a different conduction type are diffused in a diffusedregion formed on surface of a semiconductor substrate to form anotherdiffused region and a difference in the horizontal diffusion betweenthese diffused regions is employed as an effective channel length. Thisstructure, in which a short channel is formed, can constitute an elementwith low “on” resistance.

FIGS. 11A and 11B are a sectional view for explaining a conventionalLDMOS transistor. A N-channel LDMOS transistor structure is illustrated.Although the structure of a P-channel LDMOS transistor structure is notexplained here, it is well known that the same structure can be adoptedexcept for its conduction type.

In FIG. 11A, reference numeral 1 denotes a semiconductor substrate witha first conduction type, e.g. P-type, and reference numeral 2 denotes aP-type well region. A P-type body region 3 is formed within the P-typewell region 1. An N-type diffused region 4 is formed within the P-typebody region 3. Another N-type diffused region 5 is formed apart from theN-type diffused region 4. A gate electrode 7 is formed on the surface ofthe substrate 1 through a gate insulating film 6. A channel region 8 isformed in the surface region of the P-type body region 3 immediatelybelow the gate electrode.

The N-type diffused region 4 is used as a source region whereas theN-type diffused region is used as a drain region. The N-type well region2 below a LOCOS oxide film 9 is used as a drift region. Further,reference numerals 10 and 11 denote a source electrode and drainelectrode, respectively. Reference numeral 12 denotes a P-type diffusedregion for assuming the potential of the P-type body region 3 andreference numeral 13 denotes an interlayer insulating film.

In the above LDMOS transistor, since the N-type well region 2 is formedby diffusion, a high impurity concentration is given on the surface ofthe N-type well region, a current is apt to flow in the surface of theN-type well region, thereby realizing a high withstand voltage. TheLDMOS transistor having such a configuration is referred to as a surfacerelax type (RESURF)LDMOS. The dopant concentration of the drift regionin the N-type well region 2 is set so as to satisfy the condition ofRESURF. Such a technique is disclosed in JP-A-9-139438.

However, since the impurity concentration is high in the surface of theN-type well region, P-type impurity for forming the P-type body region 3cannot diffuse sufficiently. Therefore, as shown in FIG. 11B, the edgeof the P-type body region 3 approaches the source region (N-typediffused region 4) so that the channel region 8 may be not be formed tohave a suitable size (see indicated arrow A).

SUMMARY OF THE INVENTION

An object of the invention is to provide a method of manufacturing asemiconductor device which can satisfy the requirements of a highwithstand voltage and reduced “on” resistance.

In order to solve the above problem, for example as shown in FIG. 1, afirst conduction type body region (e.g. P-type body region 3) is formedby ion-implanting first conduction type impurities (e.g. boron ions)using as a mask a gate electrode patterned so that its side wall istapered to be more narrow toward the top. Further, a second conductiontype source region (e.g. N-type diffused region) is formed byion-implanting second conduction type impurities (e.g. phosphorus ions)using as a mask the gate electrode 7A. In this way, by using the taperedshape of the gate electrode 7A as a mask during the ion-implantation andcontrolling a depth of the implantation, relative positions can beoptimized among the P-type body region 3, source region and channelregion 8.

In accordance with the invention, in an LDMOS transistor in which twokinds of impurities with different conduction types are diffused using agate electrode as a mask and a difference in the horizontal diffusionbetween diffused regions is employed as an effective channel length, thegate electrode is patterned so that its side wall is tapered to be morenarrow toward the top. In this configuration, it is possible to theproblem that the impurities with an opposite conduction type adjacent tothe drift region cannot diffuse sufficiently owing to the surfaceconcentration of the drift region so that the channel region cannot beformed properly.

In accordance with the invention, the drift region is formed using adifference in the diffusion length is used between at least two kinds ofsecond conduction type impurities with different diffusion coefficientsand at least one kind of first conduction type impurities having adiffusion coefficient approximately equal to or larger than at least onekind of the second conduction impurities. This simplifies a process ofmanufacturing the semiconductor device.

Further, in accordance with the invention, since the gate electrode isstructured so that its side wall is tapered to be more narrow toward thetop, it is possible to overcome the danger that when the conductive filmformed on the entire substrate surface inclusive of the gate electrodefor the gate electrode of the other transistor to be formed on the samesubstrate is patterned for removal, the conductive film is left on theside wall of the gate electrode, thereby giving rise to poorshort-circuiting.

The above and other objects and features of the invention will be moreapparent from the following description taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 to 8 are sectional views for explaining a method ofmanufacturing a semiconductor device according to an embodiment of theinvention; and

FIG. 9 is a graph showing concentration of various ions for explainingthe theory of forming a drift region according to the invention; and

FIGS. 10A and 10B are theoretical views of a method of manufacturing thesemiconductor device according to the invention; and

FIG. 11 is a sectional view of a conventional semiconductor device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Now referring to the drawings, an explanation will be given of anembodiment of a semiconductor device according to the invention and amethod of manufacturing it.

FIG. 1 is a sectional view for explaining a LDMOS transistor accordingto the invention. A N-channel LDMOS transistor structure is illustrated.Although the structure of a P-channel LDMOS transistor structure is notexplained here, it is well known that the same structure can be adoptedexcept for its conduction type.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate with afirst conduction type, e.g. P-type, and reference numeral 21 denotes aP-type well region. Within the P-type well region 21, an N⁻ layer 22 anda P-type body region 3 are formed. An N-type diffused region 4 is formedwithin the P-type body region 3. Another N-type diffused region 5 isformed apart from the N-type diffused region 4. A gate electrode 7A isformed on the surface of the substrate 1 through a gate insulating film6. A channel region 8 is formed in the surface region of the P-type bodyregion 3 immediately below the gate electrode.

The N-type diffused region 4 is used as a source region whereas theN-type diffused region is used as a drain region. The N-type well region2 below a LOCOS oxide film 9 is used as a drift region. Although notillustrated, like the conventional structure, a source electrode 10 anda drain electrode 11 are formed in contact with the N-type diffusedregions 4 and 5. A P-type diffused region 12 for assuming the potentialof the P-type body region 3 is formed so as to be adjacent to the N-typediffused region 4, and is covered with an interlayer insulating film 13.

The feature of the invention resides in the shape of the gate electrode7A. Namely, as seen from FIG. 1, the gate electrode is patterned so thatits side wall is tapered to be more narrow toward the top. Because ofthe presence of the gate electrode 7A having such a shape, asemiconductor device can be provided in which optimum relative positionsare set among the P-type body region 3, source region 4 and channelregion 8, as described in detail. Specifically, when the firstconduction type impurities (e.g. boron ions) are ion-implanted using thegate electrode 7A having a tapered shape thereby to form the P-type bodyregion 3, the boron ions penetrate the tapered gate electrode so thatthey are also ion-implanted below the gate electrode 7A. Thus, as shownin FIG. 1, the P-type body region 3, which could not diffusesufficiently owing to the N-well region 2 which constitutes a driftregion in the conventional structure (FIG. 11B) (corresponding to N−layer 22 in the present structure), can diffuse sufficiently. Inaddition, since the second conduction type impurities (e.g. phosphorusions) are ion-implanted using the gate electrode 7A as a mask thereby toform an N-type diffused region 4 (constituting a source region), it ispossible to solve the problem involved with the conventionalsemiconductor device that the P-type body region cannot diffusesufficiently owing to hindrance of the N-well region 2 so that thechannel region cannot be formed.

In the semiconductor device according to the invention, the N⁻ layer 22is formed within the P-type well region 21. The N⁻ layer 22 is formed soas to be shallow below the gate electrode 7A (first N⁻ layer 22A) anddeep in the vicinity of the drain region 5 (second N⁻ layer 22B).

The configuration provides a further RESURF effect as compared with theconventional device. The first N⁻ layer 22A formed at a deep positionbelow the gate electrode 7A, which has a high impurity concentration,provides reduced “on” resistance so that a current is apt to flowtherefrom. In addition, the second N⁻ layer 22B which is formed in thevicinity of the drain region (drift region), which has a low impurityconcentration, is likely to enlarge a depletion layer, thereby realizingthe high withstand voltage of the transistor (see the graph of FIG. 9showing the distribution of impurity concentration). Incidentally, theN-channel LDMOS transistor according to this embodiment has a withstandvoltage of about 30 V. The invention can be applied to a semiconductordevice which has a high RESURF effect and the P-type body region 3 islikely to diffuse insufficiently because of the presence of the driftregion (first N⁻ layer).

Now referring to the drawings, an explanation will be given of a methodof manufacturing a semiconductor device according to the invention.

First, in FIG. 2, after a pad oxide film 30 has been formed on a P-typesemiconductor substrate 1, using a photoresist film 31 as a mask, twokinds of N-type impurities (e.g. arsenic ions and phosphorus ions) areion-implanted into a P type well region 21 to form a first ion-implantedlayer 32 (one-dot chain line) and a second ion-implanted layer 33(dotted line). These N-type impurities serve to form an N⁻ layer 22constituting a drift region in later steps. In this step, the arsenicions are implanted under the condition of an accelerating voltage ofabout 160 KeV and a dose of 3×10¹²/cm², whereas the phosphorus ions areimplanted under the conduction of the accelerating voltage of about 50KeV and dose of 4×10¹²/cm².

In FIG. 3, using a silicon nitride film (not shown) formed on thesubstrate as a mask, a certain region of the substrate surface isselectively oxidized to form LOCOS oxide films 9 each having a thicknessof about 7300 A. Simultaneously, because of a difference in thediffusion coefficient between the diffused arsenic ions and phosphorusions, the arsenic ions are diffused into the substrate 1 so that thefirst N⁻ layer 22 (illustrated one-dot chain line) is formed in arelatively substrate-surface layer. The phosphorus ions are diffusedinto the substrate 1 so that the second N− layer 22B (illustrated bysolid line) is formed at a relatively deep position in the P type wellregion 21.

In FIG. 4, after a photoresist film 34 has been formed on the substrate1 of a region where a drain is to be formed (referred to as“drain-forming region”), using the photoresist film 34 as a mask, P-typeimpurities (e.g. boron ions) are ion-implanted in the substrate-surfacelayer of a region where a source is to be formed (referred to as“source-forming region) and diffused. Thus, the phosphorus ions formingthe second N⁻ layer 22B in the source forming region are canceled by theboron ions so that the second N⁻ layer in the source forming region iscaused to disappear. In this step, for example, after the boron ions areimplanted under the condition of an accelerating voltage of 80 KeV anddose of 8×10¹²/cm², they are thermally diffused for two hours. Now, FIG.9 is a graph showing the distribution of the impurity concentration whenarsenic ions (illustrated by solid line), phosphorus ions (illustratedby dotted line) and boron ions (illustrated by one-dot chain line) arediffused, respectively. As seen from the graph, the concentrationdistribution originating from the phosphorus ions are canceled by itsmerging with that from the boron ions.

In this way, in accordance with the present invention, using thedifference in a diffusion coefficient between the arsenic ions andphosphorus ions when the drift region is formed, the second N⁻ layer 22Bof the source-forming region formed at a deep position of the substrateis caused to disappear by diffusing the boron ions implanted in thesubsequent step. Thus, only the first N⁻ layer 22A formed in thesubstrate surface layer is left in the source-forming region.Accordingly, the semiconductor device with reduced “on” resistancereduced can be manufactured through a relatively simple manufacturingprocess.

In FIG. 5, after a gate insulating film 6 having a thickness of 800 A isformed on the substrate, a gate electrode having a thickness of 2500 Ais formed so that it extends from the gate insulating film 6 to theLOCOS oxide film 9 and its side wall is tapered to be more narrow towardthe top. Referring to the theoretical view of FIG. 10, an explanationwill be given of a method of forming the gate electrode 7A having atapered shape according to the invention.

First, as shown in FIG. 10A, after a polysilicon film (which may bereplaced by an amorphous silicon film) on the gate insulating film 6 onthe substrate 1, the polysilicon film is doped with phosphorus from athermal diffusion source of e.g. POCl₃ and made conductive. Further,impurities (e.g. phosphorus ions) are ion-implanted in only the surfacelayer of the polysilicon film made conductive (see xxx mark in FIG.10A). In this step, the phosphorus ions can be ion-implanted under thecondition of a low accelerating voltage of about 30-40 KeV and arelatively high concentration of 1-2×10¹⁵/cm2.

Next, as shown in FIG. 10B, using a photoresist mask formed on thepolysilicon film 17 as a mask, the polysilicon film 17 is isotropicallyetched by an CDE (chemical dry etching) apparatus. Thus, a gateelectrode 7A is formed which is patterned so that its side wall istapered to be more narrow toward the top.

In this step, by ion-implanting the impurities previously on the surfaceof a conductive film for forming the gate electrode 7A, the isotropywhen the conductive film is etched could be enhanced to provide a taperhaving a relatively uniform gradient. Additionally, the etchingcondition such as the thickness of the conductive film and etching gasmay be optimized so that a recessed area of the surface, which may beprovided by the normal isotropic etching, is not given even when theion-implantation step of the above impurities is not executed. Thetapered shape should not be limited to a comparatively uniform gradient,but may be defined in various shapes in connection with the implantingcondition of boron ions for forming the P-type body region 3 in a laterstep.

Next, in FIG. 6, using, as a mask, a photoresist film 35 formed so as tocover the gate electrode 7 and drain forming region, P-type impurities(e.g. boron ions) are implanted and diffused, thereby forming the P-typebody region 3 to be adjacent to the one edge of the gate electrode 7A.(The one edge of the gate electrode 7A is exposed of the photoresist.)Incidentally, in this step, after the boron ions have been implantedunder the condition of an accelerating voltage of about 40 KeV and doseof 5×10¹³/cm², they are thermally diffused for two hours at 1050° C. Atthis time, using the tapered shape of the gate electrode 7A, the boronions are implanted in the substrate surface layer so as to penetratethrough the gate electrode 7A. Thus, it is possible to solve theconventional problem that the P-type body region 3 diffusesinsufficiently owing to the presence of the N⁻ layer so that the channelregion 8 having a suitable size cannot be formed when a source region(N-type diffused region 4) is formed in a later step.

In this way, the minimum change in the manufacturing process of changingthe pattered shape of the gate electrode 7A permits the above problem tobe solved.

The following techniques can be proposed in order to solve the aboveproblem. First, a technique can be proposed which increases the dose ofboron ions in the P-type body region 3. However, this techniqueexcessively increases the concentration of the P-type body region 3,thereby also increasing the threshold voltage. This hinders realizationof the low on-resistance which is a feature of the LDMOS transistor.Secondly, another technique can be proposed which changes the thermalprocessing during the diffusion of the P-type body region 3. However,this technique varies the impurity concentration distribution of anothertransistor (the DMOS transistor is not necessarily required), and hencerequires a considerable process change of setting the impurityconcentration distribution again.

As described above, the above proposed techniques have disadvantages. Onthe other hand, the invention can solve the problem without doing theconsiderable process change. In addition, the P-type body region 3having various shapes can be formed by only adjusting the acceleratingenergy at the time of implantation of boron ions in accordance with theshape of the gate electrode 7A.

Returning to the process of manufacturing the semiconductor device, inFIG. 7, using, as a mask, a photoresist mask 37 having openings on thesource region to be formed in the P-type body region 3 and the drainregion, N-type impurities are diffused to form N-type diffused regions 4and 5 which constitute the source and drain regions, respectively. Inthis step, where the source/drain regions are formed having an LDDstructure, first, with the photoresist film 35 removed in FIG. 6, forexample, phosphorus ions are implanted under the condition of anaccelerating voltage of 40 KeV and dose of 3.5×10¹³/cm², as shown inFIG. 7, a side wall spacer film 36 is formed on the side wall of thegate electrode 7. Using the photoresist film 37 as a mask, for example,arsenic ions are implanted under the condition of an acceleratingvoltage of 80 KeV and dose of 5×10¹⁵/cm². Incidentally, in thisembodiment, it is needless to say that the source/drain region shouldnot be limited to the LDD structure. Further, in the structure of thegate electrode 7A having a tapered shape according to the invention, acertain degree of the gradient may not provide the side wall spacer 36.However, this step of implanting the arsenic ions is necessary to formthe source/drain regions in an LDD structure for another transistor (theother transistor than the DMOS transistor may be adopted) formed in thesame substrate.

In FIG. 8, in order to form a P-type diffused region 12 adjacent to theN-type diffused region for the purpose of assuming the potential of theP-type body region 3, using a photoresist film as a mask, P-typeimpurities (e.g. boron difluoride ions) are implanted to form the P-typediffused region 12. In this step, the boron difluoride ions areimplanted under the conduction of an accelerating voltage of 60 KeV anddose of 4×10¹⁵/cm².

Subsequently, like the conventional structure, after the sourceelectrode 10 and drain electrode 11 have been formed, an interlayerinsulating film 13 is formed to complete the semiconductor device.

As described hitherto, in accordance with the invention, the gateelectrode 7A is patterned so that its side wall is tapered to be morenarrow toward the top. Because of the presence of the gate electrode 7Ahaving such a shape, a semiconductor device can be provided in whichoptimum relative positions are set among the P-type body region 3,source region 3 and channel 8. Specifically, when boron ions areion-implanted using the gate electrode 7A having a tapered shape therebyto form the P-type body region 3, the boron ions penetrate the taperedgate electrode so that they are also ion-implanted below the gateelectrode 7A. Thus, the P-type body region 3, which could not diffusesufficiently owing to the drift region in the conventional structure candiffuse sufficiently. Accordingly, the P-type body region 3 is diffusedand formed suitably so that the channel region can be formed properly.

Since the gate electrode 7A according to the invention is structured sothat its side wall is tapered to be more narrow toward the top, it ispossible to overcome the danger that when the conductive film formed onthe entire substrate surface inclusive of the gate electrode 7A for thegate electrode of the other transistor to be formed on the samesubstrate is patterned for removal, the conductive film is left on theside wall of the gate electrode 7A, thereby giving rise to poorshort-circuiting.

Although in the above embodiments photoresist is used as a mask, it isnot required to be limited to photoresist, organic mask or non-organicmask pattered by lazer irradiating can be used effectively.

What is claimed is:
 1. A semiconductor device comprising: a gateelectrode patterned on a gate insulating film on a first conduction typesemiconductor substrate; a first conduction type body region formedadjacent to the gate electrode; a second conduction type source regionand a channel region which are formed within said first conduction typebody region; a drain region formed apart from said first conduction typebody region; and a second conduction type drift region formed betweenthe channel region and drain region so as to be shallow below the gateelectrode and deep in the vicinity of the drain region, wherein a sidewall of the gate electrode on a side of the source region is tapered. 2.A semiconductor device according to claim 1, wherein the semiconductordevice further comprises a first conduction type well region formedwithin the first conduction type semiconductor substrate.
 3. Asemiconductor device according to claim 1, wherein said first conductiontype body region is a first conduction type impurity diffusion regionformed by implanting first conduction type impurities by using said gateelectrode as a mask.
 4. A semiconductor device according to claim 1,wherein said first conduction type body region is a first conductiontype impurity diffusion region formed by implanting first conductiontype impurities by using said gate electrode as a mask and said secondconduction type source region is a second conduction type impuritydiffusion region formed by second conduction type impurities by usingthe gate electrode as a mask.
 5. A semiconductor device according toclaim 1, wherein said second conduction type drift region is a secondconduction type impurity diffusion region formed by using a differencein the diffusion length between at least two kinds of second conductiontype impurities with different diffusion coefficients and at least onekind of first conduction type impurities having a diffusion coefficientapproximately equal to or larger than at least one kind of the secondconduction type impurities.
 6. A semiconductor device comprising: afirst conduction type semiconductor substrate; a gate insulating filmdisposed on the first conduction type semiconductor substrate; a gateelectrode provided on the gate insulating film, the gate electrodehaving a tapered side wall; a first conduction type body region formedadjacent to the gate electrode; a second conduction type source regionand a channel region which are formed within said first conduction typebody region; a drain region formed apart from said first conduction typebody region; and a second conduction type drift region formed betweenthe channel region and the drain region, and the drift region having ashallow portion disposed below the gate electrode and a deep portiondisposed in the vicinity of the drain region, wherein the shallowportion of the drift region is entirely disposed below the gateelectrode.
 7. A semiconductor device comprising: a first conduction typesemiconductor substrate; a gate insulating film disposed on the firstconduction type semiconductor substrate; a gate electrode provided onthe gate insulating film, the gate electrode having a tapered side wall;a first conduction type body region formed adjacent to the gateelectrode; a second conduction type source region and a channel regionwhich are formed within the first conduction type body region; a drainregion formed apart from said first conduction type body region; and asecond conduction type drift region formed between the channel regionand the drain region, and the drift region having a shallow portiondisposed below the gate electrode and a deep portion disposed in thevicinity of the drain region, wherein the gate insulating film has afirst insulating portion having a first thickness and a secondinsulating portion having a second thickness, the first thickness islarger than the second thickness, wherein the a shallow portion of thedrift region is disposed entirely below the gate electrode.